Reducing DRAM Access Latency by Exploiting DRAM Leakage Characteristics and Common Access Patterns

TL;DR

This paper introduces ChargeCache, a low-cost mechanism that reduces DRAM access latency by exploiting the charge retention of recently-accessed rows, improving system performance and energy efficiency without hardware modifications.

Contribution

The paper proposes ChargeCache, a novel memory controller technique that tracks recently-accessed DRAM rows to enable faster access based on their charge state, without modifying DRAM hardware.

Findings

ChargeCache reduces DRAM latency significantly.

It improves system performance across various workloads.

It decreases energy consumption in memory operations.

Abstract

DRAM-based memory is a critical factor that creates a bottleneck on the system performance since the processor speed largely outperforms the DRAM latency. In this thesis, we develop a low-cost mechanism, called ChargeCache, which enables faster access to recently-accessed rows in DRAM, with no modifications to DRAM chips. Our mechanism is based on the key observation that a recently-accessed row has more charge and thus the following access to the same row can be performed faster. To exploit this observation, we propose to track the addresses of recently-accessed rows in a table in the memory controller. If a later DRAM request hits in that table, the memory controller uses lower timing parameters, leading to reduced DRAM latency. Row addresses are removed from the table after a specified duration to ensure rows that have leaked too much charge are not accessed with lower latency. We evaluate ChargeCache on a wide variety of workloads and show that it provides significant performance and energy benefits for both single-core and multi-core systems.