Low Complexity Multiply Accumulate Unit for Weight-Sharing Convolutional Neural Networks

TL;DR

This paper introduces a low-complexity MAC unit for weight-sharing CNNs that replaces multipliers with adders, reducing hardware size and power consumption while maintaining performance.

Contribution

A novel MAC circuit design that leverages weight binning in CNNs to minimize hardware complexity and power use.

Findings

Fewer gates and smaller logic compared to traditional MAC units.

Reduced power consumption in the proposed MAC design.

Maintains same clock speed performance as conventional units.

Abstract

Convolutional Neural Networks (CNNs) are one of the most successful deep machine learning technologies for processing image, voice and video data. CNNs require large amounts of processing capacity and memory, which can exceed the resources of low power mobile and embedded systems. Several designs for hardware accelerators have been proposed for CNNs which typically contain large numbers of Multiply Accumulate (MAC) units. One approach to reducing data sizes and memory traffic in CNN accelerators is "weight sharing", where the full range of values in a trained CNN are put in bins and the bin index is stored instead of the original weight value. In this paper we propose a novel MAC circuit that exploits binning in weight-sharing CNNs. Rather than computing the MAC directly we instead count the frequency of each weight and place it in a bin. We then compute the accumulated value in a subsequent multiply phase. This allows hardware multipliers in the MAC circuit to be replaced with adders and selection logic. Experiments show that for the same clock speed our approach results in fewer gates, smaller logic, and reduced power.