A parallel pattern for iterative stencil + reduce

TL;DR

This paper introduces the Loop-of-stencil-reduce pattern, a unified approach for simplifying data-parallel programming on heterogeneous multi-core systems, enabling flexible deployment of stencil computations across different GPUs.

Contribution

It proposes the Loop-of-stencil-reduce pattern as a general, reusable abstraction that encompasses various parallel computation patterns and demonstrates its implementation in the FastFlow framework.

Findings

Pattern simplifies implementation of data-parallel programs.

Enables deployment of a single kernel across different GPUs.

Experiments show effective use in heterogeneous systems.

Abstract

We advocate the Loop-of-stencil-reduce pattern as a means of simplifying the implementation of data-parallel programs on heterogeneous multi-core platforms. Loop-of-stencil-reduce is general enough to subsume map, reduce, map-reduce, stencil, stencil-reduce, and, crucially, their usage in a loop in both data-parallel and streaming applications, or a combination of both. The pattern makes it possible to deploy a single stencil computation kernel on different GPUs. We discuss the implementation of Loop-of-stencil-reduce in FastFlow, a framework for the implementation of applications based on the parallel patterns. Experiments are presented to illustrate the use of Loop-of-stencil-reduce in developing data-parallel kernels running on heterogeneous systems.