Design of a Ternary Edge-Triggered D Flip-Flap-Flop for Multiple-Valued Sequential Logic

TL;DR

This paper introduces a novel ternary D Flip-Flap-Flop that allows customization by eliminating unnecessary outputs, resulting in power savings, and is validated through HSPICE simulations in 45 nm CMOS technology.

Contribution

A new ternary D Flip-Flap-Flop design enabling output customization for power efficiency, validated with detailed simulations.

Findings

Significant power reduction compared to previous designs

Successful simulation and testing with HSPICE in 45 nm CMOS technology

Flexible design allowing elimination of unused outputs

Abstract

Development of large computerized systems requires both combinational and sequential circuits. Registers and counters are two important examples of sequential circuits, which are widely used in practical applications like CPUs. The basic element of sequential logic is Flip-Flop, which stores an input value and returns two outputs (Q and Q_bar). This paper presents an innovative ternary D Flip-Flap-Flop, which offers circuit designers to customize their design by eliminating one of the outputs if it is not required. This unique feature of the new design leads to considerable power reduction in comparison with the previously presented structures. The proposed design is simulated and tested by HSPICE and 45 nm CMOS technology.