Thermal analysis of Josephson junctions array in cryocooler

TL;DR

This paper investigates thermal management solutions for Josephson junction arrays in cryocoolers, aiming to enable cryogen-free quantum voltage standards by improving chip thermalization and interface materials.

Contribution

It evaluates different interface materials and contact configurations to enhance thermal conduction in cryocoolers for Josephson junctions, with analysis of physical constraints at cryogenic temperatures.

Findings

Indium foil improves thermal contact between chip and support.

Thermal conduction can be further enhanced by top contact.

Physical constraints of vacuum thermal contacts are analyzed.

Abstract

Complex cryogenics is still a strong limitation to the spread of quantum voltage standards and cryogen-free operation is then particularly interesting for Josephson standards. The main difficulties in He-free refrigeration are related to chip thermalization. We tested different solutions and interface materials between the chip and the cooling surface, to improve thermal conduction. Some junctions were chosen as elements to dissipate electrical power, while some others were operated as on-chip temperature sensors. Indium foil between chip and Cu support was demonstrated to provide a good thermal interface suitable for programmable voltage standard operation. However, thermal conduction can be further increased by thermal contacting the chip at the top. Finally, general physical constraints in vacuum thermal contacts are analyzed in terms of known properties of thermal interfaces at cryogenics temperatures.