Accelerating More Secure RC4 : Implementation of Seven FPGA Designs in Stages upto 8 byte per clock

TL;DR

This paper presents FPGA-based hardware architectures that significantly accelerate the RC4 encryption algorithm, incorporating security enhancements and achieving up to 8 bytes processed per clock cycle.

Contribution

It introduces new FPGA designs with multiple coprocessors and byte-processing schemes to enhance RC4 speed and security, achieving unprecedented throughput levels.

Findings

Achieved up to 8 bytes per clock throughput in FPGA implementations.

Enhanced RC4 security with an additional Post-KSA Random Shuffling process.

Demonstrated secure communication between FPGA boards using accelerated RC4.

Abstract

RC4 can be made more secured if an additional RC4-like Post-KSA Random Shuffing (PKRS) process is introduced between KSA and PRGA. It can also be made significantly faster if RC4 bytes are processed in a FPGA embedded system using multiple coprocessors functioning in parallel. The PKRS process is tuned to form as many S-boxes as required by particular design architectures involving multiple coprocessors, each one undertaking byte-by-byte processing. Following a ecent idea [1] [2] the speed of execution of each processor is also enhanced by another fold if the byte-by-byte processing is replaced by a scheme of processing two consecutive bytes together. Adopting some new innovative concepts, three hardware design architectures are proposed in a suitable FPGA embedded system involving 1, 2 and 4 coprocessors functioning in parallel and a study is made on accelerating RC4 by processing bytes in byte-by-byte mode achieving throughputs from 1-byte-in-1-clock to 4-bytes-in-1-clock. The hardware designs are appropriately upgraded to accelerate RC4 further by processing 2 onsecutive RC4 bytes together and it has been possible to achieve a maximum throughput of 8-bytes per clock in Xilinx Virtex-5 LX110t FPGA [3] architecture followed by secured data communication between two FPGA boards.