The role of the Fermi level pinning in gate tunable graphene-semiconductor junctions

TL;DR

This paper investigates how Fermi level pinning and interface trapped charges affect the electrical performance of graphene-semiconductor junctions, specifically in gate-tunable barristor devices, through a physics-based modeling approach.

Contribution

It introduces a comprehensive physics-based model that includes Fermi level pinning and bias-dependent effects to analyze barristor device performance.

Findings

Fermi level pinning significantly impacts barrier modulation.

Interface trapped charges reduce the ON-OFF current ratio.

Model predicts device behavior considering non-idealities.

Abstract

Graphene based transistors relying on a conventional structure cannot switch properly because of the absence of an energy gap in graphene. To overcome this limitation, a barristor device was proposed, whose operation is based on the modulation of the graphene-semiconductor (GS) Schottky barrier by means of a top gate, and demonstrating an ON-OFF current ratio up to $10^5$. Such a large number is likely due to the realization of an ultra clean interface with virtually no interface trapped charge. However, it is indeed technologically relevant to know the impact that the interface trapped charges might have on the barristor's electrical properties. We have developed a physics based model of the gate tunable GS heterostructure where non-idealities such as Fermi Level Pinning (FLP) and a "bias dependent barrier lowering effect" has been considered. Using the model we have made a comprehensive study of the barristor's expected digital performance.