A near-threshold RISC-V core with DSP extensions for scalable IoT Endpoint Devices

TL;DR

This paper presents an open-source near-threshold RISC-V core with DSP extensions optimized for IoT endpoint devices, achieving high energy efficiency and performance scalability in multi-core clusters.

Contribution

The paper introduces a novel NT RISC-V core with instruction extensions and microarchitectural optimizations tailored for IoT, demonstrating significant improvements in speed and energy efficiency.

Findings

3.5x faster performance on data workloads

3.2x more energy-efficient operation

Peak efficiency of 67MOPS/mW in 65nm technology

Abstract

Endpoint devices for Internet-of-Things not only need to work under extremely tight power envelope of a few milliwatts, but also need to be flexible in their computing capabilities, from a few kOPS to GOPS. Near-threshold(NT) operation can achieve higher energy efficiency, and the performance scalability can be gained through parallelism. In this paper we describe the design of an open-source RISC-V processor core specifically designed for NT operation in tightly coupled multi-core clusters. We introduce instruction-extensions and microarchitectural optimizations to increase the computational density and to minimize the pressure towards the shared memory hierarchy. For typical data-intensive sensor processing workloads the proposed core is on average 3.5x faster and 3.2x more energy-efficient, thanks to a smart L0 buffer to reduce cache access contentions and support for compressed instructions. SIMD extensions, such as dot-products, and a built-in L0 storage further reduce the shared memory accesses by 8x reducing contentions by 3.2x. With four NT-optimized cores, the cluster is operational from 0.6V to 1.2V achieving a peak efficiency of 67MOPS/mW in a low-cost 65nm bulk CMOS technology. In a low power 28nm FDSOI process a peak efficiency of 193MOPS/mW(40MHz, 1mW) can be achieved.