TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA
Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer,, Margaret Martonosi

TL;DR
This paper introduces TriCheck, a comprehensive tool for verifying memory consistency models across hardware, software, and ISA layers, ensuring correctness and uncovering issues in RISC-V implementations.
Contribution
The paper presents TriCheck, a novel full-stack verification framework for MCMs, capable of analyzing the entire hardware-software stack for consistency and correctness.
Findings
Identified under-specifications in RISC-V ISA documentation.
Detected 144 forbidden outcomes in RISC-V microarchitecture out of 1701 tests.
Showed the importance of full-stack verification for MCM correctness.
Abstract
Memory consistency models (MCMs) which govern inter-module interactions in a shared memory system, are a significant, yet often under-appreciated, aspect of system design. MCMs are defined at the various layers of the hardware-software stack, requiring thoroughly verified specifications, compilers, and implementations at the interfaces between layers. Current verification techniques evaluate segments of the system stack in isolation, such as proving compiler mappings from a high-level language (HLL) to an ISA or proving validity of a microarchitectural implementation of an ISA. This paper makes a case for full-stack MCM verification and provides a toolflow, TriCheck, capable of verifying that the HLL, compiler, ISA, and implementation collectively uphold MCM requirements. The work showcases TriCheck's ability to evaluate a proposed ISA MCM in order to ensure that each layer and each…
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