Design-Space Exploration and Optimization of an Energy-Efficient and Reliable 3D Small-world Network-on-Chip
Sourav Das, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu, Chakrabarty

TL;DR
This paper introduces a machine-learning-inspired design methodology for 3D Network-on-Chip architectures that enhances energy efficiency and reliability, outperforming traditional mesh-based designs through innovative small-world network topologies and spare-vertical link allocation.
Contribution
It proposes a novel 3D small-world network-on-chip design and a computationally efficient reliability enhancement algorithm, advancing the state-of-the-art in energy-efficient and reliable 3D NoC architectures.
Findings
3D SWNoC achieves 35% energy-delay-product improvement over 3D MESH.
The spare-vertical link allocation algorithm significantly improves reliability and lifetime.
Small-world topology outperforms traditional mesh in performance metrics.
Abstract
A three-dimensional (3D) Network-on-Chip (NoC) enables the design of high performance and low power many-core chips. Existing 3D NoCs are inadequate for meeting the ever-increasing performance requirements of many-core processors since they are simple extensions of regular 2D architectures and they do not fully exploit the advantages provided by 3D integration. Moreover, the anticipated performance gain of a 3D NoC-enabled many-core chip may be compromised due to the potential failures of through-silicon-vias (TSVs) that are predominantly used as vertical interconnects in a 3D IC. To address these problems, we propose a machine-learning-inspired predictive design methodology for energy-efficient and reliable many-core architectures enabled by 3D integration. We demonstrate that a small-world network-based 3D NoC (3D SWNoC) performs significantly better than its 3D MESH-based…
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