ASIC Design of a Noisy Gradient Descent Bit Flip Decoder for 10GBASE-T Ethernet Standard

TL;DR

This paper presents an ASIC implementation of a noisy gradient descent bit flip decoder for 10GBASE-T Ethernet, achieving high throughput, low area, and energy efficiency with improved error performance.

Contribution

The paper introduces a fully parallel ASIC design of the NGDBF decoder with two-phase operation, optimizing latency, area, and energy efficiency for high-speed Ethernet.

Findings

Achieves >10Gbps throughput at medium/high SNRs

Consumes 0.81mm² area and 1.7pJ/bit energy

Outperforms existing decoders in area and energy efficiency

Abstract

In this paper, the NGDBF algorithm is implemented on a code that is deployed in the IEEE 802.3an Ethernet standard. The design employs a fully parallel architecture and operates in two-phases: start-up phase and decoding phase. The two phase operation keeps the high latency operations off-line, thereby reducing the decoding latency during the decoding phase. The design is bench-marked with other state-of-the-art designs on the same code that employ different algorithms and architectures. The results indicate that the NGDBF decoder has a better area efficiency and a better energy efficiency compared to other state-of-art decoders. When the design is operated in medium to high signal to noise ratios, the design is able to provide greater than the required minimum throughput of 10Gbps. The design consumes 0.81mm2 of area and has an energy efficiency of 1.7pJ/bit, which are the lowest in the reported literature. The design also provides better error performance compared to other simplified decoder implementations and consumes lesser wire-length compared to a recently proposed design.