FPGA Design for Pseudorandom Number Generator Based on Chaotic Iteration used in Information Hiding Application

TL;DR

This paper presents an FPGA-based chaotic iteration generator for high-speed, cryptographically secure pseudorandom numbers, improving efficiency and demonstrating application in information hiding security.

Contribution

It introduces an optimized FPGA implementation of a chaotic iteration-based pseudorandom generator, enhancing speed and security for information hiding applications.

Findings

High generation rate achieved on FPGA

Generator produces statistically good chaotic random bits

Secure for cryptographic applications

Abstract

Lots of researches indicate that the inefficient generation of random numbers is a significant bottleneck for information communication applications. Therefore, Field Programmable Gate Array (FPGA) is developed to process a scalable fixed-point method for random streams generation. In our previous researches, we have proposed a technique by applying some well-defined discrete chaotic iterations that satisfy the reputed Devaney's definition of chaos, namely chaotic iterations (CI). We have formerly proven that the generator with CI can provide qualified chaotic random numbers. In this paper, this generator based on chaotic iterations is optimally redesigned for FPGA device. By doing so, the generation rate can be largely improved. Analyses show that these hardware generators can also provide good statistical chaotic random bits and can be cryptographically secure too. An application in the information hiding security field is finally given as an illustrative example.