Towards Predictable Real-Time Performance on Multi-Core Platforms

TL;DR

This paper addresses the challenge of achieving predictable real-time performance on multi-core platforms in cyber-physical systems by developing analytical and system techniques to bound and reduce resource contention-induced delays.

Contribution

It introduces novel analytical bounds and system-level primitives to mitigate temporal interference, enabling predictable real-time performance on modern multi-core platforms.

Findings

Temporal interference can cause up to 12x delay on commodity hardware.

Proposed techniques effectively bound and reduce resource contention delays.

Enhanced predictability for safety-critical cyber-physical systems.

Abstract

Cyber-physical systems (CPS) integrate sensing, computing, communication and actuation capabilities to monitor and control operations in the physical environment. A key requirement of such systems is the need to provide predictable real-time performance: the timing correctness of the system should be analyzable at design time with a quantitative metric and guaranteed at runtime with high assurance. This requirement of predictability is particularly important for safety-critical domains such as automobiles, aerospace, defense, manufacturing and medical devices. The work in this dissertation focuses on the challenges arising from the use of modern multi-core platforms in CPS. Even as of today, multi-core platforms are rarely used in safety-critical applications primarily due to the temporal interference caused by contention on various resources shared among processor cores, such as caches, memory buses, and I/O devices. Such interference is hard to predict and can significantly increase task execution time, e.g., up to 12x on commodity quad-core platforms. To address the problem of ensuring timing predictability on multi-core platforms, we develop novel analytical and systems techniques in this dissertation. Our proposed techniques theoretically bound temporal interference that tasks may suffer from when accessing shared resources. Our techniques also involve software primitives and algorithms for real-time operating systems and hypervisors, which significantly reduce the degree of the temporal interference. Specifically, we tackle the issues of cache and memory contention, locking and synchronization, interrupt handling, and access control for computational accelerators such as GPGPUs, all of which are crucial to achieving predictable real-time performance on a modern multi-core platform.