Scalable gate architecture for densely packed semiconductor spin qubits

TL;DR

This paper presents a scalable linear gate architecture for densely packed semiconductor spin qubits, demonstrated with a 12 quantum dot device on Si/SiGe, showing reproducible control, charge sensing, and fast two-qubit operation potential.

Contribution

The work introduces a novel scalable gate architecture for semiconductor quantum dots, validated with a 12-dot device demonstrating key quantum control features.

Findings

Reproducible single quantum dot energies with less than 20% variation.

Charge sensors with high sensitivity enabling real-time charge dynamics.

Potential for 50 GHz two-qubit gate operation speeds.

Abstract

We demonstrate a 12 quantum dot device fabricated on an undoped Si/SiGe heterostructure as a proof-of-concept for a scalable, linear gate architecture for semiconductor quantum dots. The device consists of 9 quantum dots in a linear array and 3 single quantum dot charge sensors. We show reproducible single quantum dot charging and orbital energies, with standard deviations less than 20% relative to the mean across the 9 dot array. The single quantum dot charge sensors have a charge sensitivity of 8.2 x 10^{-4} e/root(Hz) and allow the investigation of real-time charge dynamics. As a demonstration of the versatility of this device, we use single-shot readout to measure a spin relaxation time T1 = 170 ms at a magnetic field B = 1 T. By reconfiguring the device, we form two capacitively coupled double quantum dots and extract a mutual charging energy of 200 microeV, which indicates that 50 GHz two-qubit gate operation speeds are feasible.