Novel Graph Processor Architecture, Prototype System, and Results

TL;DR

This paper introduces a novel FPGA-based graph processor architecture with innovative features like a sparse matrix instruction set and cacheless memory, significantly improving graph computation throughput over traditional processors.

Contribution

It presents a new parallel graph processor architecture with unique hardware innovations and an FPGA prototype demonstrating superior performance.

Findings

Significant performance enhancement over conventional processors.

Effective handling of large graph datasets.

Innovative architecture components like systolic sorter and high-bandwidth network.

Abstract

Graph algorithms are increasingly used in applications that exploit large databases. However, conventional processor architectures are inadequate for handling the throughput and memory requirements of graph computation. Lincoln Laboratory's graph-processor architecture represents a rethinking of parallel architectures for graph problems. Our processor utilizes innovations that include a sparse matrix-based graph instruction set, a cacheless memory system, accelerator-based architecture, a systolic sorter, high-bandwidth multi-dimensional toroidal communication network, and randomized communications. A field-programmable gate array (FPGA) prototype of the new graph processor has been developed with significant performance enhancement over conventional processors in graph computational throughput.