FPGA based hybrid architecture for parallelizing RRT
Gurshaant Malik, Krishna Gupta, Raunak Dharani, K Madhava Krishna

TL;DR
This paper presents a hybrid FPGA architecture combining combinatorial and hierarchical designs to accelerate RRT algorithms, achieving high performance-per-watt for robotics applications.
Contribution
It introduces a novel hybrid FPGA architecture for RRT, optimizing module allocation via a cost function and modified branch and bound for improved efficiency.
Findings
Hybrid architecture outperforms standalone designs in speed and power efficiency.
Optimal module allocation enhances performance-per-watt for different kinematic models.
The approach is validated on differential, quad-copter, and fixed wing scenarios.
Abstract
Field Programmable Gate Arrays(FPGA) exceed the computing power of software based implementations by breaking the paradigm of sequential execution and accomplishing more per clock cycle by enabling hardware level parallelization at an architectural level. Introducing parallel architectures for a computationally intensive algorithm like Rapidly Exploring Random Trees(RRT) will result in an exploration that is fast, dense and uniform. Through a cost function delineated in later sections, FPGA based combinatorial architecture delivers superlative speed-up but consumes very high power while hierarchical architecture delivers relatively lower speed-up with acceptable power consumption levels. To combine the qualities of both, a hybrid architecture, that encompasses both combinatorial and hierarchical architecture, is designed. To determine the number of RRT nodes to be allotted to the…
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Taxonomy
TopicsEmbedded Systems Design Techniques · Parallel Computing and Optimization Techniques · Algorithms and Data Compression
