Processing In-memory realization using Quantum Dot Cellular Automata

TL;DR

This paper demonstrates a quantum-dot-based in-memory computing architecture using QCA and Akers array, achieving reduced power, smaller size, and faster computation for NAND and NOR gates.

Contribution

It introduces a novel QCA-based PIM architecture with primitive cells smaller than CMOS, enhancing speed and power efficiency.

Findings

Minimum power dissipation for gates

Primitive cell size of 0.04 micron^2

Improved speed and reduced power consumption

Abstract

The present manuscript deals with the realization of Processing In-memory (PIM) computing architecture using Quantum Dot Cellular Automata (QCA) and Akers array. The PIM computing architecture becomes popular due to its effective framework for storage and computation of data in a single unit. Here, we illustrate two input NAND and NOR gate with the help of QCA based Akers Array as a case study. The QCA flip-flop is used as a primitive cell to design PIM architecture. The results suggested that both the gate have minimum power dissipation. The polarization results of proposed architecture suggested that the signals are in good control. The foot print of the primitive cell equals to 0.04 micron^2, which is smaller than conventional CMOS primitive cell. The combination of QCA and Akers array provides many additional benefits over the conventional architecture like reduction in the power consumption and feature size, furthermore, it also improves the computational speed.