A Modular Data Acquisition System using the 10 GSa/s PSEC4 Waveform Recording Chip

TL;DR

This paper presents a modular, high-speed data acquisition system utilizing the PSEC4 waveform recording chip, featuring multi-channel architecture, FPGA control, and scalable channel management for large detector arrays.

Contribution

It introduces a scalable, multi-level hardware system with FPGA-based control and data processing, enabling high-speed, multi-channel waveform acquisition with flexible configuration.

Findings

Supports up to 1920 channels of PSEC4 with a single VME crate.

Achieves analog bandwidth of 1.5 GHz per channel.

Provides flexible data readout options including USB, Ethernet, and SFP links.

Abstract

We describe a modular multi-channel data acquisition system based on the 5-15 Gigasample-per-second waveform-recording PSEC4 chip. The system architecture incorporates two levels of hardware with FPGA-embedded system control and in-line data processing. The front-end unit is a 30-channel circuit board that holds five PSEC4 ASICs, a clock jitter cleaner, and a control FPGA. The analog bandwidth of the front-end signal path is 1.5 GHz. Each channel has an on-chip threshold-level discriminator that is monitored in the FPGA, from which a flexible on-board trigger decision can be formed. To instrument larger channel counts, a `back-end' 6U VME32 control card has been designed. Called the 'Central Card', it incorporates an Altera Arria-V FPGA that manages up to 8 front-end cards using one or two CAT5 network cables per board, which transmits the clock and communicates data packets over a custom serial protocol. Data can be read from the Central Card via USB, Ethernet, or dual SFP links, in addition to the VME interface. The Central Card can be configured as either Master or Slave, allowing one Master to receive data from up to 8 Slaves, with each Slave managing 8 30-channel front-end cards, allowing a single VME crate to control up to 1920 channels of the PSEC4 chip.