Improvement of the Orthogonal Code Convolution Capabilities Using FPGA Implementation

TL;DR

This paper presents an FPGA-based method to significantly enhance the error detection capabilities of orthogonal codes, achieving near-perfect detection and improved correction of multiple errors.

Contribution

A novel FPGA implementation that increases the error detection rate of orthogonal codes by about 50%, enabling more reliable data transmission.

Findings

Error detection improved to approximately 99.9%

Corrects up to (n/4-1) bits of error

Bandwidth efficiency maintained

Abstract

When data is stored, compressed, or communicated through a media such as cable or air, sources of noise and other parameters such as EMI, crosstalk, and distance can considerably affect the reliability of these data. Error detection and correction techniques are therefore required. Orthogonal Code is one of the codes that can detect errors and correct corrupted data. An n-bit orthogonal code has n/2 1s and n/2 0s. In a previous work these properties have been exploited to detect and correct errors. In this paper we present a new methodology to enhance error detection capabilities of the orthogonal code. The technique was implemented experimentally using Field Programmable Gate Arrays (FPGA). The results show that the proposed technique improves the detection capabilities of the orthogonal code by approximately 50%, resulting in 99.9% error detection, and corrects as predicted up to (n/4-1) bits of error in the received impaired code with bandwidth efficiency.