Maximizing CNN Accelerator Efficiency Through Resource Partitioning

TL;DR

This paper introduces a resource partitioning approach for FPGA-based CNN accelerators, creating specialized processors for different CNN layers, significantly boosting throughput compared to traditional single-processor designs.

Contribution

The paper proposes a novel resource partitioning methodology that divides FPGA resources into multiple specialized processors for CNN layers, improving efficiency and throughput.

Findings

Achieved 3.8x throughput increase on AlexNet

Realized 2.2x and 2.0x speedups on SqueezeNet and GoogLeNet

Demonstrated superior performance over state-of-the-art designs

Abstract

Convolutional neural networks (CNNs) are revolutionizing machine learning, but they present significant computational challenges. Recently, many FPGA-based accelerators have been proposed to improve the performance and efficiency of CNNs. Current approaches construct a single processor that computes the CNN layers one at a time; the processor is optimized to maximize the throughput at which the collection of layers is computed. However, this approach leads to inefficient designs because the same processor structure is used to compute CNN layers of radically varying dimensions. We present a new CNN accelerator paradigm and an accompanying automated design methodology that partitions the available FPGA resources into multiple processors, each of which is tailored for a different subset of the CNN convolutional layers. Using the same FPGA resources as a single large processor, multiple smaller specialized processors increase computational efficiency and lead to a higher overall throughput. Our design methodology achieves 3.8x higher throughput than the state-of-the-art approach on evaluating the popular AlexNet CNN on a Xilinx Virtex-7 FPGA. For the more recent SqueezeNet and GoogLeNet, the speedups are 2.2x and 2.0x.