Device and Circuit Interaction Analysis of Stochastic Behaviors in Cross-Point RRAM Arrays

TL;DR

This paper analyzes the stochastic behaviors in cross-point RRAM arrays, developing a Monte Carlo model to evaluate how device variability and array design influence write failure probability and energy efficiency.

Contribution

It introduces a calibrated Monte Carlo SPICE model for oxide RRAM and proposes a pseudo-sub-array topology to improve variation tolerance and reduce energy consumption.

Findings

Array size and wire resistance worsen write failure probability.

Lowering VDD increases energy consumption due to higher WFP.

Pseudo-sub-array topology reduces WFP and EEC, enhancing capacity.

Abstract

Stochastic behaviors of resistive random access memory (RRAM) play an important role in the design of cross-point memory arrays. A Monte Carlo compact model of oxide RRAM is developed and calibrated with experiments on various device stack configurations. With Monte Carlo SPICE simulations, we show that an increase in array size and interconnect wire resistance will statistically deteriorate write functionality. Write failure probability (WFP) has an exponential dependency on device uniformity and supply voltage (VDD), and the array bias scheme is a key knob. Lowering array VDD leads to higher effective energy consumption (EEC) due to the increase in WFP when the variation statistics are included in the analysis. Random-access simulations indicate that data sparsity statistically benefits write functionality and energy consumption. Finally, we show that a pseudo-sub-array topology with uniformly distributed pre-forming cells in the pristine high resistance state is able to reduce both WFP and EEC, enabling higher net capacity for memory circuits due to improved variation tolerance.