Program Execution on Reconfigurable Multicore Architectures
Sanjiva Prasad (Indian Institute of Technology Delhi, New Delhi,, India)

TL;DR
This paper explores a reconfigurable multicore architecture that adaptively changes its configuration to optimize performance for different application phases, while analyzing the semantic preservation and efficiency of such reconfigurations.
Contribution
It introduces a formal framework for reconfigurable multicore architectures, ensuring semantic preservation and efficiency analysis during dynamic reconfiguration.
Findings
Reconfiguration can preserve program semantics under certain conditions.
A partial ordering of configurations helps determine safe reconfiguration paths.
Amortised bisimulation measures execution efficiency across configurations.
Abstract
Based on the two observations that diverse applications perform better on different multicore architectures, and that different phases of an application may have vastly different resource requirements, Pal et al. proposed a novel reconfigurable hardware approach for executing multithreaded programs. Instead of mapping a concurrent program to a fixed architecture, the architecture adaptively reconfigures itself to meet the application's concurrency and communication requirements, yielding significant improvements in performance. Based on our earlier abstract operational framework for multicore execution with hierarchical memory structures, we describe execution of multithreaded programs on reconfigurable architectures that support a variety of clustered configurations. Such reconfiguration may not preserve the semantics of programs due to the possible introduction of race conditions…
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Taxonomy
TopicsParallel Computing and Optimization Techniques · Embedded Systems Design Techniques · Distributed systems and fault tolerance
