Large-Signal Model of Graphene Field-Effect Transistors -- Part I: Compact Modeling of GFET Intrinsic Capacitances

TL;DR

This paper introduces a comprehensive, circuit-compatible large-signal model for GFETs, including intrinsic capacitances and a drift-diffusion-based drain current, enabling accurate simulation of their electrical behavior in circuits.

Contribution

It presents the first compact, charge-conserving intrinsic capacitance model for GFETs integrated with a drift-diffusion drain current model, implemented in Verilog-A.

Findings

Model accurately simulates DC, transient, and frequency response behaviors.

Intrinsic capacitance matrix includes 16 elements with charge conservation.

Implementation in Verilog-A ensures compatibility with circuit simulators.

Abstract

We present a circuit-compatible compact model of the intrinsic capacitances of graphene field-effect transistors (GFETs). Together with a compact drain current model, a large-signal model of GFETs is developed combining both models as a tool for simulating the electrical behavior of graphene-based integrated circuits, dealing with the DC, transient behavior, and frequency response of the circuit. The drain current model is based in a drift-diffusion mechanism for the carrier transport coupled with an appropriate field-effect approach. The intrinsic capacitance model consists of a 16-capacitance matrix including self-capacitances and transcapacitances of a four-terminal GFET. To guarantee charge conservation, a Ward-Dutton linear charge partition scheme has been used. The large-signal model has been implemented in Verilog-A, being compatible with conventional circuit simulators and serving as a starting point toward the complete GFET device model that could incorporate additional non-idealities.