Hardware-Based ADMM-LP Decoding
Mitchell Wasson, Mario Milicevic, Stark C. Draper, Glenn Gulak

TL;DR
This paper introduces an FPGA-based fixed-point implementation of an ADMM-LP decoder for error correction, demonstrating improved scalability and performance, especially in high-SNR error floor regimes, compared to traditional LP solvers.
Contribution
It presents the first hardware-based fixed-point implementation of an ADMM-LP decoder, enhancing scalability and performance over previous floating-point versions.
Findings
Hardware implementation achieves competitive decoding speed.
Fixed-point design maintains decoding accuracy.
Improved error floor performance in high-SNR regimes.
Abstract
In this paper we present an FPGA-based implementation of linear programming (LP) decoding. LP decoding frames error correction as an optimization problem. This is in contrast to variants of belief propagation (BP) decoding that view error correction as a problem of graphical inference. There are many advantages to taking the optimization perspective: convergence guarantees, improved performance in certain regimes, and a methodology for incorporating the latest developments in optimization techniques. However, LP decoding, when implemented with standard LP solvers, does not easily scale to the blocklengths of modern error-correction codes. In earlier work, we showed that by drawing on decomposition methods from optimization theory, specifically the alternating direction method of multipliers (ADMM), we could build an LP decoding solver that was competitive with BP, both in terms of…
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Taxonomy
TopicsError Correcting Code Techniques · Advanced Wireless Communication Techniques · Optical Network Technologies
