Hardware Based Projection onto The Parity Polytope and Probability Simplex

TL;DR

This paper develops and adapts efficient algorithms for Euclidean norm projections onto the parity polytope and probability simplex for hardware implementation, demonstrating their scalability and accuracy on FPGA devices.

Contribution

It refines projection algorithms for the parity polytope and adapts them for hardware, achieving scalable resource usage and computational efficiency.

Findings

Algorithms achieve $ ext{O}(d)$ or $ ext{O}(d ext{log}d)$ complexity

Hardware implementations scale as $ ext{O}(d( ext{log}d)^2)$ in area

Numerical results show good fixed-point accuracy and resource scaling

Abstract

This paper is concerned with the adaptation to hardware of methods for Euclidean norm projections onto the parity polytope and probability simplex. We first refine recent efforts to develop efficient methods of projection onto the parity polytope. Our resulting algorithm can be configured to have either average computational complexity $\mathcal{O}\left(d\right)$ or worst case complexity $\mathcal{O}\left(d\log{d}\right)$ on a serial processor where $d$ is the dimension of projection space. We show how to adapt our projection routine to hardware. Our projection method uses a sub-routine that involves another Euclidean projection; onto the probability simplex. We therefore explain how to adapt to hardware a well know simplex projection algorithm. The hardware implementations of both projection algorithms achieve area scalings of $\mathcal{O}(d\left(\log{d}\right)^2)$ at a delay of $\mathcal{O}(\left(\log{d}\right)^2)$. Finally, we present numerical results in which we evaluate the fixed-point accuracy and resource scaling of these algorithms when targeting a modern FPGA.