Coding for Improved Throughput Performance in Network Switches

TL;DR

This paper investigates how coding strategies in network switches can significantly enhance throughput by optimizing packet placement and memory utilization, supported by new algorithms and analytical tools.

Contribution

It introduces a novel placement policy called 'design placement' that maximizes throughput and efficiency in coded network switches.

Findings

Design placement achieves high throughput and feasible implementation.

Coding upon write improves memory utilization for read operations.

Analytical tools evaluate throughput gains of different placement policies.

Abstract

Network switches and routers need to serve packet writes and reads at rates that challenge the most advanced memory technologies. As a result, scaling the switching rates is commonly done by parallelizing the packet I/Os using multiple memory units. For improved read rates, packets can be coded upon write, thus giving more flexibility at read time to achieve higher utilization of the memory units. This paper presents a detailed study of coded network switches, and in particular how to design them to maximize the throughput advantages over standard uncoded switches. Toward that objective the paper contributes a variety of algorithmic and analytical tools to improve and evaluate the throughput performance. The most interesting finding of this study is that the placement of packets in the switch memory is the key to both high performance and algorithmic efficiency. One particular placement policy we call "design placement" is shown to enjoy the best combination of throughput performance and implementation feasibility.