Secure and trusted white-box verification
Yixian Cai, George Karakostas, Alan Wassyng

TL;DR
This paper introduces protocols for verifying designs with limited information disclosure, enabling secure, trusted, and flexible verification by third parties without revealing sensitive design details.
Contribution
It formalizes limited information verification using tabular expressions and develops protocols for white-box testing that work with trusted or untrusted developers.
Findings
Protocols enable verification with partial design info
Verification process can be checked by third parties
Works with both trusted and untrusted developers
Abstract
Verification is the process of checking whether a product has been implemented according to its prescribed specifications. We study the case of a designer (the developer) that needs to verify its design by a third party (the verifier), by making publicly available a limited amount of information about the design, namely a diagram of interconnections between the different design components, but not the components themselves or the intermediate values passed between components. We formalize this notion of limited information using tabular expressions as the description method for both the specifications and the design. Treating verification as a process akin to testing, we develop protocols that allow for the design to be verified on a set of inputs generated by the verifier, using any test-case generating algorithm that can take advantage of this extra available information (partially…
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Taxonomy
TopicsCryptography and Data Security · Physical Unclonable Functions (PUFs) and Hardware Security · Formal Methods in Verification
