A Fault Tolerance Improved Majority Voter for TMR System Architectures

TL;DR

This paper introduces a new fault-tolerant majority voter for TMR systems that is more robust against internal and external faults, while also reducing power, delay, and area in nanoelectronic implementations.

Contribution

A novel fault-tolerant majority voter design that improves robustness and efficiency in nanoelectronic TMR architectures, considering simultaneous faults.

Findings

Enhanced fault tolerance against multiple simultaneous faults.

Reduced power dissipation, delay, and area compared to existing voters.

Validated through simulation on 32/28nm CMOS technology.

Abstract

For digital system designs, triple modular redundancy (TMR), which is a 3-tuple version of N-modular redundancy is widely preferred for many mission-control and safety-critical applications. The TMR scheme involves two-times duplication of the simplex system hardware, with a majority voter ensuring correctness provided at least two out of three copies of the system remain operational. Thus the majority voter plays a pivotal role in ensuring the correct operation of the system. The fundamental assumption implicit in the TMR scheme is that the majority voter does not become faulty, which may not hold well for implementations based on latest technology nodes with dimensions of the order of just tens of nanometers. To overcome the drawbacks of the classical majority voter some new voter designs were put forward in the literature with the aim of enhancing the fault tolerance. However, these voter designs generally ensure the correct system operation in the presence of either a faulty function module or the faulty voter, considered only in isolation. Since multiple faults may no longer be excluded in the nanoelectronics regime, simultaneous fault occurrences on both the function module and the voter should be considered, and the fault tolerance of the voters have to be analyzed under such a scenario. In this context, this article proposes a new fault-tolerant majority voter which is found to be more robust to faults than the existing voters in the presence of faults occurring internally and/or externally to the voter. Moreover, the proposed voter features less power dissipation, delay, and area metrics based on the simulation results obtained by using a 32/28nm CMOS process.