CORDIC-based Architecture for Powering Computation in Fixed-Point Arithmetic

TL;DR

This paper introduces a fixed-point hardware architecture based on the hyperbolic CORDIC algorithm for powering computations, enabling optimized trade-offs among resources, accuracy, and execution time.

Contribution

It presents a fully customizable CORDIC-based architecture with a design space exploration method to generate Pareto-optimal hardware solutions.

Findings

Achieved Pareto-optimal trade-offs between resource usage and accuracy.

Demonstrated flexibility in design parameters for optimized performance.

Provided VHDL source code for practical implementation.

Abstract

We present a fixed point architecture (source VHDL code is provided) for powering computation. The fully customized architecture, based on the expanded hyperbolic CORDIC algorithm, allows for design space exploration to establish trade-offs among design parameters (numerical format, number of iterations), execution time, resource usage and accuracy. We also generate Pareto-optimal realizations in the resource-accuracy space: this approach can produce optimal hardware realizations that simultaneously satisfy resource and accuracy requirements.