Efficient Execution of Irregular Wavefront Propagation Pattern on Many Integrated Core Architecture

TL;DR

This paper presents optimized implementations of the Irregular Wavefront Propagation Pattern algorithm on Many Integrated Core architectures, achieving significant speedups and enabling processing of larger images.

Contribution

It introduces SIMD-optimized, parallel, and heterogeneous implementations of IWPP, improving performance and scalability on MIC architectures compared to prior GPU-based methods.

Findings

Up to 5.63x speedup with vectorization

Up to 55x speedup with parallel FIFO queue implementation

Performance 1.62x better than existing GPU implementations

Abstract

The efficient execution of image processing algorithms is an active area of Bioinformatics. In image processing, one of the classes of algorithms or computing pattern that works with irregular data structures is the Irregular Wavefront Propagation Pattern (IWPP). In this class, elements propagate information to neighbors in the form of wave propagation. This propagation results in irregular access to data and expansions. Due to this irregularity, current implementations of this class of algorithms requires atomic operations, which is very costly and also restrains implementations with Single Instruction, Multiple Data (SIMD) instructions in Many Integrated Core (MIC) architectures, which are critical to attain high performance on this processor. The objective of this study is to redesign the Irregular Wavefront Propagation Pattern algorithm in order to enable the efficient execution on processors with Many Integrated Core architecture using SIMD instructions. In this work, using the Intel (R) Xeon Phi (TM) coprocessor, we have implemented a vector version of IWPP with up to 5.63x gains on non-vectored version, a parallel version using First In, First Out (FIFO) queue that attained speedup up to 55x as compared to the single core version on the coprocessor, a version using priority queue whose performance was 1.62x better than the fastest version of GPU based implementation available in the literature, and a cooperative version between heterogeneous processors that allow to process images bigger than the Intel (R) Xeon Phi (TM) memory and also provides a way to utilize all the available devices in the computation.