VLSI Extreme Learning Machine: A Design Space Exploration

TL;DR

This paper presents a compact, low-power VLSI implementation of the Extreme Learning Machine (ELM) that explores the design trade-offs between speed, power, and accuracy, demonstrating high efficiency and scalability.

Contribution

It introduces a novel hardware design for ELM using current mirror mismatch for vector-matrix multiplication and an input rotation method to extend input dimensions beyond physical chip limits.

Findings

Achieves 0.47 pJ/MAC energy efficiency at 31.6 kHz classification rate.

Demonstrates effective regression and classification on UCI datasets.

Provides a design space exploration balancing speed, power, and accuracy.

Abstract

In this paper, we describe a compact low-power, high performance hardware implementation of the extreme learning machine (ELM) for machine learning applications. Mismatch in current mirrors are used to perform the vector-matrix multiplication that forms the first stage of this classifier and is the most computationally intensive. Both regression and classification (on UCI data sets) are demonstrated and a design space trade-off between speed, power and accuracy is explored. Our results indicate that for a wide set of problems, $\sigma V_T$ in the range of $15-25$mV gives optimal results. An input weight matrix rotation method to extend the input dimension and hidden layer size beyond the physical limits imposed by the chip is also described. This allows us to overcome a major limit imposed on most hardware machine learners. The chip is implemented in a $0.35 \mu$m CMOS process and occupies a die area of around 5 mm $\times$ 5 mm. Operating from a $1$ V power supply, it achieves an energy efficiency of $0.47$ pJ/MAC at a classification rate of $31.6$ kHz.