An Integrated Circuit for Radio Astronomy Correlators Supporting Large Arrays of Antennas

TL;DR

This paper presents a low-power, integrated circuit design capable of performing digital cross-correlations for large antenna arrays in radio astronomy, significantly reducing power and cost for large N.

Contribution

The authors introduce a scalable IC architecture with 4096 CMAC units optimized for large antenna arrays, enabling efficient correlation computations in radio telescopes.

Findings

Supports 64 signals in parallel with 4096 CMAC units

Achieves energy efficiency of 1.76 to 3.3 pJ per CMAC operation

Suitable for fabrication in 32 nm SOI process, with less than 12 mm² area

Abstract

Radio telescopes that employ arrays of many antennas are in operation, and ever larger ones are being designed and proposed. Signals from the antennas are combined by cross-correlation. For $N$ antennas, the cost and power consumption of cross-correlation are proportional to $N^2$ and dominate at sufficiently large $N$. Here we report the design of an integrated circuit (IC) that performs digital cross-correlations for arbitrarily many antennas in a power-efficient way. It uses an intrinsically low-power architecture in which the movement of data between devices is minimized. In our design, the correlations are performed in an array of 4096 complex multiply-accumulate (CMAC) units. This is sufficient to perform all correlations in parallel for 64 signals ($N$=32 antennas with 2 opposite-polarization signals per antenna). When $N$ is larger, the input data are buffered in an on-chip memory and the CMACs are re-used as many times as needed to compute all correlations. The design has been synthesized and simulated so as to obtain accurate estimates of the IC's size and power consumption. It is intended for fabrication in a 32 nm silicon-on-insulator process, where it will require less than 12 mm$^2$ of silicon area and achieve an energy efficiency of 1.76 to 3.3 pJ per CMAC operation, depending on the number of antennas. Operation has been analyzed in detail up to $N=4096$. The system-level energy efficiency, including board-level I/O, power supplies, and controls, is expected to be 5 to 7 pJ per CMAC operation.