Enhanced Circuit Densities in Epitaxially Defined FinFETs (EDFinFETs) over FinFETs

TL;DR

This paper proposes EDFinFETs, a new transistor architecture that significantly reduces variability and enables taller fins, allowing for comparable or higher circuit density than traditional FinFETs despite larger device footprints.

Contribution

It introduces EDFinFET architecture, demonstrating reduced variability and the ability to engineer multiple STI levels for improved circuit density.

Findings

Reduces LER-based VT variability by 90%.

Enables taller fins for multiple STI levels.

Achieves equal or higher circuit density despite larger device footprints.

Abstract

FinFET technology is prone to suffer from Line Edge Roughness (LER) based VT variation with scaling. To address this, we proposed an Epitaxially Defined (ED) FinFET (EDFinFET) as an alternate to FinFET architecture for 10 nm node and beyond. We showed by statistical simulations that EDFinFET reduces LER based VT variability by 90% and overall variability by 59%. However, EDFinFET consists of wider fins as the fin widths are not constrained by electrostatics and variability (cf. FinFETs have fin width ~ LG/3 where LG is gate-length). This indicates that EDFinFET based circuits may be less dense. In this study we show that wide fins enable taller fin heights. The ability to engineer multiple STI levels on tall fins enables different transistor widths (i.e. various W/Ls e.g. 1-10) in a single fin. This capability ensures that even though individual EDFinFET devices have ~2x larger footprints than FinFETs, EDFinFET may produce equal or higher circuit density for basic building blocks like inverters or NAND gates for W/Ls of 2 and higher.