A Direct Mapping of Max k-SAT and High Order Parity Checks to a Chimera Graph

TL;DR

This paper presents a method to directly map max k-SAT and high-order parity check problems onto the Chimera graph of D-Wave quantum annealers, enabling applications in decoding and satisfiability problem solving.

Contribution

It introduces a direct mapping technique from max k-SAT and parity check problems to Chimera graphs, expanding the range of problems solvable by quantum annealing hardware.

Findings

Mapping preserves low energy spectrum of problems

Applicable to decoding turbo codes near Shannon limit

Enables solving general satisfiability problems on Chimera hardware

Abstract

We demonstrate a direct mapping of max k-SAT problems (and weighted max k-SAT) to a Chimera graph, which is the non-planar hardware graph of the devices built by D-Wave Systems Inc. We further show that this mapping can be used to map a similar class of maximum satisfiability problems where the clauses are replaced by parity checks over potentially large numbers of bits. The latter is of specific interest for applications in decoding for communication. We discuss an example in which the decoding of a turbo code, which has been demonstrated to perform near the Shannon limit, can be mapped to a Chimera graph. The weighted max k-SAT problem is the most general class of satisfiability problems, so our result effectively demonstrates how any satisfiability problem may be directly mapped to a Chimera graph. Our methods faithfully reproduce the low energy spectrum of the target problems, so therefore may also be used for maximum entropy inference.