Effect of Jitter on the Settling Time of Mesochronous Clock Retiming Circuits

TL;DR

This paper investigates how timing jitter affects the settling time of mesochronous clock recovery circuits, models the phenomenon with Markov chains, and proposes techniques to reduce settling time using mismatched correction strengths and a coarse+fine retiming approach.

Contribution

It introduces a Markov chain model for jitter-induced settling time and proposes novel techniques to significantly reduce settling time in mesochronous clock retiming circuits.

Findings

Mismatched correction strengths can reduce settling time by up to 40%.

The proposed coarse+fine retiming circuit achieves faster settling.

Model predictions match behavioral simulation results.

Abstract

It is well known that timing jitter can degrade the bit error rate (BER) of receivers that recover the clock from input data. However, timing jitter can also result in an indefinite increase in the settling time of clock recovery circuits, particularly in low swing mesochronous systems. Mesochronous clock retiming circuits are required in repeaterless low swing on-chip interconnects. We first discuss how timing jitter can result in a large increase in the settling time of the clock recovery circuit. Next, the circuit is modelled as a Markov chain with absorbing states. The mean time to absorption of the Markov chain, which represents the mean settling time of the circuit, is determined. The model is validated through behavioural simulations of the circuit, the results of which match well with the model predictions. We consider circuits with (i) data dependent jitter, (ii) random jitter, and (iii) combination of both of them. We show that a mismatch between the strengths of up and down corrections of the retiming can reduce the settling time. In particular, a 10% mismatch can reduce the mean settling time by up to 40%. We leverage this fact toward improving the settling time performance, and propose useful techniques based on biased training sequences and mismatched charge pumps. We also present a coarse+fine clock retiming circuit, which can operate in coarse first mode, to reduce the settling time substantially. These fast settling retiming circuits are verified with circuit simulations.