Lock-in range of PLL-based circuits with proportionally-integrating filter and sinusoidal phase detector characteristic

TL;DR

This paper investigates the lock-in range of PLL-based circuits with sinusoidal phase detectors and PI filters, providing rigorous definitions and both numerical and analytical estimates for this key synchronization characteristic.

Contribution

It introduces a rigorous mathematical definition of lock-in range and offers new numerical and analytical estimates for PLL-based circuits with specific configurations.

Findings

Rigorous mathematical definition of lock-in range

Numerical estimates for lock-in range

Analytical estimates for lock-in range

Abstract

In the present work PLL-based circuits with sinusoidal phase detector characteristic and active proportionally-integrating (PI) filter are considered. The notion of lock-in range -- an important characteristic of PLL-based circuits, which corresponds to the synchronization without cycle slipping, is studied. For the lock-in range a rigorous mathematical definition is discussed. Numerical and analytical estimates for the lock-in range are obtained.