CVC Verilog Compiler -- Fast Complex Language Compilers Can be Simple

TL;DR

This paper presents a method for developing fast Verilog HDL simulators using flow graph compilation and the von Neumann architecture, achieving high performance with minimal code and demonstrating the effectiveness of anti-formalist approaches.

Contribution

It introduces a novel approach to Verilog simulation based on flow graph compilation and anti-formalism, resulting in a highly efficient simulator with minimal code.

Findings

Developed the fastest IEEE 1364 Verilog HDL simulator with 95,000 lines of C code.

Validated the anti-formalist methodology in computer science through practical implementation.

Demonstrated that detailed abstraction removal is not necessary for high-speed Verilog simulation.

Abstract

This paper explains how to develop Verilog hardware description language (HDL) optimized flow graph compiled simulators. It is claimed that the methods and algorithms described here can be applied in the development of flow graph compilers for other complex computer languages. The method uses the von Neumann computer architecture (MRAM model) as the best abstract model of computation and uses comparison and selection of alternative machine code sequences to utilize modern processor low level parallelism. By using the anti formalist method described here, the fastest available full IEEE 1364 2005 Verilog HDL standard simulators has been developed. The compiler only required 95,000 lines of C code and two developers. This paper explains how such a compiled simulator validates the anti-formalism computer science methodology best expressed by Peter Naur's datalogy and provides specific guidelines for applying the method. Development history from a slow interpreter into a fast flow graph based machine code compiled simulator is described. The failure of initial efforts that tried to convert a full 1364 compliant interpreter into interpreted execution of possibly auto generated virtual machines is discussed. The argument that fast Verilog simulation requires detail removing abstraction is shown to be incorrect. Reasons parallel GPU Verilog simulation has not succeeded are given.