Basic circuit compilation techniques for an ion-trap quantum machine

TL;DR

This paper presents a comprehensive method for compiling quantum algorithms into optimized physical circuits suitable for ion-trap quantum computers, focusing on reducing gate counts and errors while allowing flexible trade-offs.

Contribution

It introduces a complete multi-stage compilation strategy tailored for ion-trap quantum machines, emphasizing optimization of gate counts, runtime, and error minimization without fault-tolerance layers.

Findings

Effective reduction of two-qubit gate count.

Flexible optimization trade-offs demonstrated.

Enhanced circuit performance for ion-trap systems.

Abstract

We study the problem of compilation of quantum algorithms into optimized physical-level circuits executable in a quantum information processing (QIP) experiment based on trapped atomic ions. We report a complete strategy: starting with an algorithm in the form of a quantum computer program, we compile it into a high-level logical circuit that goes through multiple stages of decomposition into progressively lower-level circuits until we reach the physical execution-level specification. We skip the fault-tolerance layer, as it is not within the scope of this work. The different stages are structured so as to best assist with the overall optimization while taking into account numerous optimization criteria, including minimizing the number of expensive two-qubit gates, minimizing the number of less expensive single-qubit gates, optimizing the runtime, minimizing the overall circuit error, and optimizing classical control sequences. Our approach allows a trade-off between circuit runtime and quantum error, as well as to accommodate future changes in the optimization criteria that may likely arise as a result of the anticipated improvements in the physical-level control of the experiment.