A Reconfigurable Low Power High Throughput Architecture for Deep Network Training

TL;DR

This paper introduces a reconfigurable multicore architecture utilizing memristor crossbars to achieve low power, high throughput deep neural network training and recognition, significantly outperforming traditional GPGPU systems in energy efficiency.

Contribution

The paper presents a novel memristor-based multicore architecture for deep neural networks that enhances energy efficiency and throughput for training and inference tasks.

Findings

Up to five orders of magnitude energy efficiency improvement over GPGPUs.

Supports both training and recognition for neural networks.

Applicable to classification, feature extraction, and anomaly detection.

Abstract

General purpose computing systems are used for a large variety of applications. Extensive supports for flexibility in these systems limit their energy efficiencies. Neural networks, including deep networks, are widely used for signal processing and pattern recognition applications. In this paper we propose a multicore architecture for deep neural network based processing. Memristor crossbars are utilized to provide low power high throughput execution of neural networks. The system has both training and recognition (evaluation of new input) capabilities. The proposed system could be used for classification, dimensionality reduction, feature extraction, and anomaly detection applications. The system level area and power benefits of the specialized architecture is compared with the NVIDIA Telsa K20 GPGPU. Our experimental evaluations show that the proposed architecture can provide up to five orders of magnitude more energy efficiency over GPGPUs for deep neural network processing.