Design and Implementation of an Improved Carry Increment Adder

TL;DR

This paper presents an improved carry increment adder that enhances speed by integrating a carry look-ahead adder, demonstrated through Verilog HDL simulations, offering better performance over traditional designs.

Contribution

The paper introduces a novel design of carry increment adder using carry look-ahead adder to reduce delay, improving upon previous ripple carry adder-based designs.

Findings

Reduced delay in adder circuit performance.

Successful implementation in Verilog HDL.

Enhanced speed compared to traditional CIA designs.

Abstract

A complex digital circuit comprises of adder as a basic unit. The performance of the circuit depends on the design of this basic adder unit. The speed of operation of a circuit is one of the important performance criteria of many digital circuits which ultimately depends on the delay of the basic adder unit. Many research works have been devoted in improving the delay of the adder circuit. In this paper we have proposed an improved carry increment adder (CIA) that improves the delay performance of the circuit. The improvement is achieved by incorporating carry look adder (CLA) in the design of CIA contrary to the previous design of CIA that employs ripple carry adder (RCA). A simulation study is carried out for comparative analysis. The coding is done in Verilog hardware description language (HDL) and the simulation is carried out in Xilinx ISE 13.1 environment.