A Dynamic Overlay Supporting Just-In-Time Assembly to Construct Customized Hardware Accelerators

TL;DR

This paper introduces a dynamic overlay system that enables the assembly of customized hardware accelerators at runtime by composing pre-synthesized hardware operators, simplifying FPGA programming and deployment.

Contribution

It proposes a novel dynamic overlay architecture that supports Just-In-Time assembly of hardware accelerators using pre-synthesized operators for easier FPGA utilization.

Findings

Supports runtime assembly of hardware accelerators

Reduces FPGA programming complexity

Enables flexible and efficient hardware customization

Abstract

Barriers that prevent programmers from using FPGAs include the need to work within vendor specific CAD tools, knowledge of hardware programming models, and the requirement to pass each design through synthesis, place and route. In this work, a dynamic overlay is designed to support Just- In-Time assembly by composing hardware operators to construct full accelerators. The hardware operators are pre-synthesized bit- streams and can be downloaded to Partially Reconfigurable(PR) regions at runtime.