Conformal Titanium Nitride in a Porous Silicon Matrix: a Nanomaterial for In-Chip Supercapacitors

TL;DR

This paper presents a novel in-chip supercapacitor using porous silicon coated with titanium nitride, achieving high capacitance, energy density, and stability, enabling integrated energy storage within silicon microchips.

Contribution

The study introduces a new nanomaterial combining porous silicon and titanium nitride for integrated supercapacitors, demonstrating high performance and compatibility with chip fabrication.

Findings

High specific capacitance of 15 F/cm³

Energy density of 1.3 mWh/cm³

Power density up to 214 W/cm³

Abstract

Today's supercapacitor energy storages are typically discrete devices aimed for printed boards and power applications. The development of autonomous sensor networks and wearable electronics and the miniaturisation of mobile devices would benefit substantially from solutions in which the energy storage is integrated with the active device. Nanostructures based on porous silicon (PS) provide a route towards integration due to the very high inherent surface area to volume ratio and compatibility with microelectronics fabrication processes. Unfortunately, pristine PS has limited wettability and poor chemical stability in electrolytes and the high resistance of the PS matrix severely limits the power efficiency. In this work, we demonstrate that excellent wettability and electro-chemical properties in aqueous and organic electrolytes can be obtained by coating the PS matrix with an ultra-thin layer of titanium nitride by atomic layer deposition. Our approach leads to very high specific capacitance (15 F/cm$^3$), energy density (1.3 mWh/cm$^3$), power density (up to 214 W/cm$^3$) and excellent stability (more than 13,000 cycles). Furthermore, we show that the PS-TiN nanomaterial can be integrated inside a silicon chip monolithically by combining MEMS and nanofabrication techniques. This leads to realisation of in-chip supercapacitor, i.e., it opens a new way to exploit the otherwise inactive volume of a silicon chip to store energy.