Complementary Skyrmion Racetrack Memory with Voltage Manipulation

TL;DR

This paper proposes a novel skyrmion-based racetrack memory design that uses voltage manipulation to improve data control and address key challenges in skyrmion memory technology, supported by micromagnetic simulations.

Contribution

It introduces a complementary skyrmion racetrack memory structure utilizing voltage control, advancing skyrmion memory design beyond current limitations.

Findings

Enhanced skyrmion manipulation demonstrated in simulations

Improved data representation and synchronization capabilities

Potential for low-power, high-density memory applications

Abstract

Magnetic skyrmion holds promise as information carriers in the next-generation memory and logic devices, owing to the topological stability, small size and extremely low current needed to drive it. One of the most potential applications of skyrmion is to design racetrack memory (RM), named Sk-RM, instead of utilizing domain wall (DW). However, current studies face some key design challenges, e.g., skyrmion manipulation, data representation and synchronization etc. To address these challenges, we propose here a complementary Sk-RM structure with voltage manipulation. Functionality and performance of the proposed design are investigated with micromagnetic simulations.