Channel Models for Multi-Level Cell Flash Memories Based on Empirical Error Analysis

TL;DR

This paper develops empirical error-based channel models for multi-level cell flash memories, demonstrating that the beta-binomial model accurately predicts ECC performance under P/E cycling stress.

Contribution

It introduces a novel beta-binomial channel model that captures overdispersion in error characteristics, improving ECC performance estimation accuracy over traditional models.

Findings

Beta-binomial model fits empirical error data well.

Traditional BAC model is insufficient for accurate ECC estimation.

Model validated with BCH, LDPC, and polar codes.

Abstract

We propose binary discrete parametric channel models for multi-level cell (MLC) flash memories that provide accurate ECC performance estimation by modeling the empirically observed error characteristics under program/erase (P/E) cycling stress. Through a detailed empirical error characterization of 1X-nm and 2Y-nm MLC flash memory chips from two different vendors, we observe and characterize the overdispersion phenomenon in the number of bit errors per ECC frame. A well studied channel model such as the binary asymmetric channel (BAC) model is unable to provide accurate ECC performance estimation. Hence we propose a channel model based on the beta-binomial probability distribution (2-BBM channel model) which is a good fit for the overdispersed empirical error characteristics and show through statistical tests and simulation results for BCH, LDPC and polar codes, that the 2-BBM channel model provides accurate ECC performance estimation in MLC flash memories.