Automatic Generation of High-Coverage Tests for RTL Designs using Software Techniques and Tools

TL;DR

This paper introduces a novel method for RTL design validation that converts RTL source code into C++, employs symbolic execution with cycle limits and bit-level support to generate high-coverage test cases, evaluated on an FPU design.

Contribution

The paper presents a new approach combining software techniques and tools, specifically symbolic execution with cycle limits and bit-level support, for effective RTL design validation.

Findings

Achieved high coverage in RTL testing.

Effective test case generation using symbolic execution.

Validated approach on an FPU design.

Abstract

Register Transfer Level (RTL) design validation is a crucial stage in the hardware design process. We present a new approach to enhancing RTL design validation using available software techniques and tools. Our approach converts the source code of a RTL design into a C++ software program. Then a powerful symbolic execution engine is employed to execute the converted C++ program symbolically to generate test cases. To better generate efficient test cases, we limit the number of cycles to guide symbolic execution. Moreover, we add bit-level symbolic variable support into the symbolic execution engine. Generated test cases are further evaluated by simulating the RTL design to get accurate coverage. We have evaluated the approach on a floating point unit (FPU) design. The preliminary results show that our approach can deliver high-quality tests to achieve high coverage.