Hardware Architecture of Complex K-best MIMO Decoder

TL;DR

This paper introduces a low-power, high-throughput hardware architecture for complex K-best MIMO decoding, improving efficiency and performance for 8x8 MIMO systems with 64 QAM modulation.

Contribution

It presents a novel VLSI design incorporating Schnorr-Euchner enumeration and Rlimit parameter to reduce complexity and enhance performance.

Findings

Achieves 1090.8 Mbps throughput

Power consumption of 782 mW

Latency of 0.044 microseconds

Abstract

This paper presents a hardware architecture of complex K-best Multiple Input Multiple Output (MIMO) decoder reducing the complexity of Maximum Likelihood (ML) detector. We develop a novel low-power VLSI design of complex K-best decoder for 8x8 MIMO and 64 QAM modulation scheme. Use of Schnorr-Euchner (SE) enumeration and a new parameter, Rlimit in the design reduce the complexity of calculating K-best nodes to a certain level with increased performance. The total word length of only 16 bits has been adopted for the hardware design limiting the bit error rate (BER) degradation to 0.3 dB with list size, K and Rlimit equal to 4. The proposed VLSI architecture is modeled in Verilog HDL using Xilinx and synthesized using Synopsys Design Vision in 45 nm CMOS technology. According to the synthesize result, it achieves 1090.8 Mbps throughput with power consumption of 782 mW and latency of 0.044 us. The maximum frequency the design proposed is 181.8 MHz.