Achieving both High Energy Efficiency and High Performance in On-Chip Communication using Hierarchical Rings with Deflection Routing
Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Kai-Wei, Chang, Greg Nazario, Reetuparna Das, Gabriel H. Loh, Onur Mutlu

TL;DR
This paper introduces HiRD, a hierarchical ring interconnect that achieves high scalability and energy efficiency without in-ring buffering by using deflection routing and simple flow control mechanisms.
Contribution
The paper presents HiRD, a hierarchical ring design that maintains simplicity while providing high scalability and energy efficiency through deflection routing and minimal buffering.
Findings
HiRD outperforms previous hierarchical ring designs in energy efficiency.
HiRD achieves comparable or better performance than traditional single rings.
The design guarantees end-to-end delivery without impacting latency for most traffic.
Abstract
Hierarchical ring networks, which hierarchically connect multiple levels of rings, have been proposed in the past to improve the scalability of ring interconnects, but past hierarchical ring designs sacrifice some of the key benefits of rings by introducing more complex in-ring buffering and buffered flow control. Our goal in this paper is to design a new hierarchical ring interconnect that can maintain most of the simplicity of traditional ring designs (no in-ring buffering or buffered flow control) while achieving high scalability as more complex buffered hierarchical ring designs. Our design, called HiRD (Hierarchical Rings with Deflection), includes features that allow us to mostly maintain the simplicity of traditional simple ring topologies while providing higher energy efficiency and scalability. First, HiRD does not have any buffering or buffered flow control within individual…
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Taxonomy
TopicsInterconnection Networks and Systems · Parallel Computing and Optimization Techniques · Low-power high-performance VLSI design
