Protection of heterogeneous architectures on FPGAs: An approach based on hardware firewalls

TL;DR

This paper proposes a hardware firewall-based security approach for heterogeneous FPGA architectures, enhancing communication protection and cryptography with low latency, demonstrated through a case study on Xilinx Virtex-6 FPGAs.

Contribution

It introduces a novel FPGA-based security method using hardware firewalls and cryptographic blocks to protect multiprocessor systems efficiently.

Findings

Up to 33% latency reduction compared to previous methods

Effective protection of communication and external memory in FPGA-based MPSoCs

Flexible cryptographic features integrated with low overhead

Abstract

Embedded systems are parts of our daily life and used in many fields. They can be found in smartphones or in modern cars including GPS, light/rain sensors and other electronic assistance mechanisms. These systems may handle sensitive data (such as credit card numbers, critical information about the host system and so on) which must be protected against external attacks as these data may be transmitted through a communication link where attackers can connect to extract sensitive information or inject malicious code within the system. This work presents an approach to protect communications in multiprocessor architectures. This approach is based on hardware security enhancements acting as firewalls. These firewalls filter all data going through the system communication bus and an additional flexible cryptographic block aims to protect external memory from attacks. Benefits of our approach are demonstrated using a case study and some custom software applications implemented in a Field-Programmable Gate Array (FPGA). Firewalls implemented in the target architecture allow getting a low-latency security layer with flexible cryptographic features. To illustrate the benefit of such a solution, implementations are discussed for different MPSoCs implemented on Xilinx Virtex-6 FPGAs. Results demonstrate a reduction up to 33% in terms of latency overhead compared to existing efforts.