Voltage Scaling of Graphene Device on SrTiO3 Epitaxial Thin Film

TL;DR

This study demonstrates that high-k SrTiO3 thin films enable voltage scaling in graphene devices, maintaining quantum Hall effects up to 200 K and reducing operating voltages without performance loss.

Contribution

It introduces the use of epitaxial SrTiO3 thin films for effective voltage scaling in graphene devices, preserving quantum phenomena at high temperatures.

Findings

Quantum Hall states survive up to 200 K at 14 T.

Significant shift in charge neutrality point correlates with dielectric constant.

Voltage reduction achieved without degrading device performance.

Abstract

Electrical transport in monolayer graphene on SrTiO3 (STO) thin film is examined in order to promote gate-voltage scaling using a high-k dielectric material. The atomically flat surface of thin STO layer epitaxially grown on Nb-doped STO single-crystal substrate offers good adhesion between the high-k film and graphene, resulting in nonhysteretic conductance as a function of gate voltage at all temperatures down to 2 K. The two-terminal conductance quantization under magnetic fields corresponding to quantum Hall states survives up to 200 K at a magnetic field of 14 T. In addition, the substantial shift of charge neutrality point in graphene seems to correlate with the temperature-dependent dielectric constant of the STO thin film, and its effective dielectric properties could be deduced from the universality of quantum phenomena in graphene. Our experimental data prove that the operating voltage reduction can be successfully realized due to the underlying high-k STO thin film, without any noticeable degradation of graphene device performance.