Phase distance mapping: a phase-based cache tuning methodology for embedded systems

TL;DR

This paper introduces phase distance mapping, a method for cache tuning in embedded systems that quickly finds near-optimal configurations for different execution phases, significantly reducing tuning overhead and improving energy-delay performance.

Contribution

It presents a novel phase distance mapping technique that eliminates the need for extensive design space exploration in phase-based cache tuning.

Findings

Determines cache configurations within 1% of optimal on average.

Achieves 27% average savings in energy-delay product.

Reduces tuning overhead in embedded system optimization.

Abstract

Networked embedded systems typically leverage a collection of low-power embedded systems (nodes) to collaboratively execute applications spanning diverse application domains (e.g., video, image processing, communication, etc.) with diverse application requirements. The individual networked nodes must operate under stringent constraints (e.g., energy, memory, etc.) and should be specialized to meet varying application requirements in order to adhere to these constraints. Phase-based tuning specializes system tunable parameters to the varying runtime requirements of different execution phases to meet optimization goals. Since the design space for tunable systems can be very large, one of the major challenges in phase-based tuning is determining the best configuration for each phase without incurring significant tuning overhead (e.g., energy and/or performance) during design space exploration. In this paper, we propose phase distance mapping, which directly determines the best configuration for a phase, thereby eliminating design space exploration. Phase distance mapping applies the correlation between the characteristics and best configuration of a known phase to determine the best configuration of a new phase. Experimental results verify that our phase distance mapping approach, when applied to cache tuning, determines cache configurations within 1 % of the optimal configurations on average and yields an energy delay product savings of 27 % on average.